INTEGRATED FUNCTIONAL AND DESIGN FOR TESTABILITY (DFT) CLOCK DELIVERY ARCHITECTURE

INTEGRATED FUNCTIONAL AND DESIGN FOR TESTABILITY (DFT) CLOCK DELIVERY ARCHITECTURE

An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: GANGADHARAN, Divya, KRISHNAPPA, Madan, NASIR, Muhammad, DAI, Hong, JAIN, Arvind
Format: Patent
Sprache:eng ; fre
Schlagworte:
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively. Un aspect de la divulgation concerne un circuit intégré (CI). Le CI comprend un premier ensemble de contrôleurs d'horloge de test (TCC) comprenant un premier ensemble de sorties d'horloge, respectivement ; et un premier ensemble de cœurs fonctionnels comprenant un premier ensemble d'entrées d'horloge couplé au premier ensemble de sorties d'horloge du premier ensemble de contrôleurs TCC, respectivement.