CHIP PACKAGE STRUCTURE, ELECTRONIC DEVICE, AND PREPARATION METHOD FOR CHIP PACKAGE STRUCTURE

Embodiments of the present application relate to the technical field of chip package, and provide a chip package structure, an electronic device, and a preparation method for a chip package structure, capable of reducing the risk of delamination of a thermal interface material (TIM). The chip package structure comprises a substrate, a plurality of chips disposed on the substrate, a heat dissipation cover disposed on the substrate and configured to dissipate heat of the plurality of chips, and a TIM layer configured to form a heat dissipation channel. The side of the central portion of the heat dissipation cover facing the substrate is provided with a protruding portion. The protruding portion abuts against the TIM layer of the chips to press the TIM layer material. Since there is a protruding portion capable of abutting against the TIM layer, after the heat dissipation cover covers the chip, when other structural parts are mounted on the heat dissipation cover, the structural parts apply pressure towards the