INTEGRATED CIRCUIT INTERCONNECTION LINE PARASITIC CAPACITANCE EXTRACTION METHOD BASED ON DISCONTINUOUS FINITE ELEMENT METHOD

The present invention belongs to the technical field of calculation, reckoning or counting. Disclosed is an integrated circuit interconnection line parasitic capacitance extraction method based on a discontinuous finite element method. The method comprises: dividing non-uniform rectangular grids according to a conductor distribution condition; determining whether the rectangular grids are boundary cells, and sequentially marking and recording global serial numbers and solution-required serial numbers; initializing degree of freedom values of all the rectangular grids; traversing all the rectangular grids, so as to obtain a linear equation system based on a discontinuous finite element method according to boundary conditions of adjacent cell grids, and calculating potential function degrees of freedom of all the rectangular grids; solving an electric-field strength function degree of freedom of each cell according to the potential function degree of freedom of each rectangular grid; and dividing a Gaussian sur