FERROELECTRIC MEMORY AND VERTICAL TRANSISTOR

The present application provides a ferroelectric memory, comprising: a substrate; word lines, a source line, a bit line and a control line; and a first ferroelectric capacitor, a first transistor and a second transistor which are stacked in the vertical direction; the first ferroelectric capacitor comprises a first electrode and a second electrode; the second electrode is exposed at the lower end and/or the upper end of the first ferroelectric capacitor; the first transistor has a first electrode connected to the source line, a second electrode connected to the bit line, and a gate in contact with the second electrode of the first ferroelectric capacitor; a channel layer of the first transistor is arranged in the vertical direction, and the gate of the first transistor forms the upper end and/or the lower end of the first transistor; the second transistor has a gate connected to the control line, a second electrode connected to the bit line, and a first electrode in contact with the second electrode of the fi