IN-CHIP INTERFERENCE TEST METHOD AND IN-CHIP INTERFERENCE TEST SYSTEM

An in-chip interference test method and test system (100). The method comprises the steps: setting up a test environment (S1) in which an input end (A1) of a first low-noise amplifier (LNA1) is connected to a first end of a first component (R1), an output end (B1) of the first low-noise amplifier (L...

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Hauptverfasser: GUO, Jiashuai, DENG, Liulei
Format: Patent
Sprache:chi ; eng ; fre
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Zusammenfassung:An in-chip interference test method and test system (100). The method comprises the steps: setting up a test environment (S1) in which an input end (A1) of a first low-noise amplifier (LNA1) is connected to a first end of a first component (R1), an output end (B1) of the first low-noise amplifier (LNA1) is connected to a second detection channel port of a vector network analyzer (E1), an input end (A2) of a second low-noise amplifier (LNA2) is connected to a first detection channel port of the vector network analyzer (E1), an output end (B2) of the second low-noise amplifier (LNA2) is connected to a first end of a second component (R2), and a signal control output end of a control device (C1) is connected to a signal control input end of a chip (U1) to be tested; supplying power and starting work (S2); acquiring an interference waveform image (S3), the first low-noise amplifier (LNA1) and the second low-noise amplifier (LNA2) being simultaneously turned on by means of the control device (C1), and an S21 param