THREE-DIMENSIONAL MEMORY, CHIP PACKAGING STRUCTURE, AND ELECTRONIC DEVICE

The present application relates to the technical field of electronic devices, and provides a three-dimensional memory, a chip packaging structure, and an electronic device. The three-dimensional memory of the present application can improve the storage capacity of a DRAM chip in a limited layout space, a manufacturing process difficulty of a capacitor in the three-dimensional memory is low, and the product qualification rate and reliability of the DRAM chip are high. Embodiments of the present application provide a three-dimensional memory comprising a substrate and a storage array layer. The storage array layer comprises at least one storage structure, and the storage structure comprises N capacitors arranged on the substrate side by side. Each capacitor comprises a first electrode, a first dielectric layer and a second electrode which are sequentially stacked on the substrate in a direction away from the substrate, wherein N is greater than or equal to 2 and N is an integer. The three-dimensional memory pro