ULTRA-LOW PHASE NOISE CLOCK BUFFER

The present invention relates to the technical field of integrated circuits, and in particular, to an ultra-low phase noise clock buffer. The ultra-low phase noise clock buffer of the present invention comprises a coupling capacitor, a first phase inverter, a first signal selector, a shaping drive circuit, and a signal channel group. The coupling capacitor is used for coupling an input signal. The first phase inverter comprises a PMOS transistor and an NMOS transistor. The trench length of the PMOS transistor and the NMOS transistor constituting the first phase inverter is not less than five times the feature size. The shaping drive circuit is used for shaping the input signal and improving the driving capability. The signal channel group comprises a plurality of signal channels. Each signal channel is used for generating a buffered and amplified output clock signal. According to the present invention, the overall structure and the unit structure of the buffer are designed, so that the phase noise can be decr