HIGH-SPEED MULTIPLEXER
A high-speed multiplexer according to an embodiment may comprise: a first stage to which a first clock signal and a data signal are input; a second stage to which a signal output from the first stage and a second clock signal are input; and a third stage including a first transistor to which a signa...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre ; kor |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Zusammenfassung: | A high-speed multiplexer according to an embodiment may comprise: a first stage to which a first clock signal and a data signal are input; a second stage to which a signal output from the first stage and a second clock signal are input; and a third stage including a first transistor to which a signal output from the second stage is input and which outputs a final signal, and a load which is connected in series to the first transistor.
Un multiplexeur à grande vitesse selon un mode de réalisation peut comprendre : un premier étage dans lequel sont entrés un premier signal d'horloge et un signal de données ; un deuxième étage dans lequel sont entrés un signal émis par le premier étage et un second signal d'horloge ; et un troisième étage comprenant un premier transistor dans lequel une sortie de signal du second étage est entrée et qui émet un signal final, et une charge qui est branchée en série au premier transistor.
일 실시예에 따른 고속 멀티플렉서는 제1클락 신호 및 데이터 신호를 입력 받는 제1스테이지, 상기 제1스테이지로부터 출력된 신호 및 제2클락 신호를 입력 받는 제2스테이지 및 상기 제2스테이지로부터 출력된 신호를 입력 받아 최종 신호를 출력하는 제1트랜지스터 및 상기 제1트랜지스터와 직렬 연결되어 있는 부하를 포함하는 제3스테이지를 포함할 수 있다. |
|---|