INSTRUCTION DISTRIBUTION METHOD AND SYSTEM IN RECONFIGURABLE PROCESSOR, AND STORAGE MEDIUM

An instruction distribution method and system in a reconfigurable processor. The reconfigurable processor comprises an instruction fetch module, an instruction synchronization control module and an instruction queue module. The method comprises: setting a storage synchronization ID table format of each instruction type (S101); obtaining a first memory identification field and a second memory identification field of each instruction (S102); obtaining one-hot codes of the first and second memory identification fields (S103); obtaining a synchronization table (S104); and executing each instruction in the multiple rows of running instruction lines (S105). According to the method, the parallel execution efficiency of multiple instructions can be ensured, the memory conflict can be reduced, and the instruction running time can be shortened. L'invention concerne un procédé et un système de distribution d'instructions dans un processeur reconfigurable. Le processeur reconfigurable comprend un module d'extraction d'in