MULTI-PHASE CLOCK GENERATION CIRCUIT

A multi-phase clock generation circuit, used for generating multi-phase non-overlapping clock signals. The multi-phase clock generation circuit comprises a loop structure formed by the input ends and output ends of a plurality of logic gates (G11, G12, G13, G14, G15, G16, G17, G18) being electrically connected end to end, and a plurality of latches (NOR21, NOR22, NOR23, NOR24, NOR25, NOR26, NOR27, NOR28) used for latching the signals of the input ends of the logic gates; the multi-phase clock generation circuit performs logic operation according to a selection signal and clock signal received by the plurality of logic gates (G11, G12, G13, G14, G15, G16, G17, G18), and latches, by means of the latches (NOR21, NOR22, NOR23, NOR24, NOR25, NOR26, NOR27, NOR28), the data of the previous-stage logic gates received by the logic gates in a loop, and outputs multi-phase non-overlapping clock signals by means of the output ends of the plurality of logic gates. From the input end to the output end of the multi-phase cl