AVALANCHE IMPACT-RESISTANT HETEROJUNCTION SEMICONDUCTOR DEVICE

Disclosed is an avalanche impact-resistant heterojunction semiconductor device. The device comprises a substrate (1) and a second dielectric layer (23). A first dielectric layer (21) is arranged on the substrate (1); a first semiconductor layer (24) is arranged on the second dielectric layer (23); a second semiconductor layer (3) is arranged on the first semiconductor layer (24); the first semiconductor layer (24) is in contact with the second semiconductor layer (3) to form a conductive channel layer (25); a metal source electrode (7), a metal gate electrode (8) and a metal drain electrode (9) are arranged on the second semiconductor layer (3); a third dielectric layer (10) is arranged between the second semiconductor layer (3) and the metal gate electrode (8), and is characterized in that: an avalanche layer is arranged between the first dielectric layer (21) and the second dielectric layer (23), and the avalanche layer is respectively connected to the metal source electrode (7) and the metal drain electrod