AN ARRAY OF VERTICAL TRANSISTORS, AN ARRAY OF MEMORY CELLS COMPRISING AN ARRAY OF VERTICAL TRANSISTORS, AND A METHOD USED IN FORMING AN ARRAY OF VERTICAL TRANSISTORS

A method used in forming an array of vertical transistors comprises forming laterally-spaced vertical projections that project upwardly from a substrate in a vertical cross-section. The vertical projections individually comprise an upper source/drain region, a lower source/drain region, and a channe...

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Bibliographische Detailangaben

Hauptverfasser:	RIGANO, Antonino, CALABRESE, Marcello, MARIANI, Marcello
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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