AN ARRAY OF VERTICAL TRANSISTORS, AN ARRAY OF MEMORY CELLS COMPRISING AN ARRAY OF VERTICAL TRANSISTORS, AND A METHOD USED IN FORMING AN ARRAY OF VERTICAL TRANSISTORS

A method used in forming an array of vertical transistors comprises forming laterally-spaced vertical projections that project upwardly from a substrate in a vertical cross-section. The vertical projections individually comprise an upper source/drain region, a lower source/drain region, and a channe...

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Hauptverfasser: RIGANO, Antonino, CALABRESE, Marcello, MARIANI, Marcello
Format: Patent
Sprache:eng ; fre
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Zusammenfassung:A method used in forming an array of vertical transistors comprises forming laterally-spaced vertical projections that project upwardly from a substrate in a vertical cross-section. The vertical projections individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. First gate insulator material is formed along opposing sidewalls of the channel region in the vertical cross- section. One of (a) or (b) is formed over opposing sidewalls of the first gate insulator material in the vertical cross-section, where (a): conductive gate lines that are horizontally elongated through the vertical cross-section; and (b): sacrificial placeholder gate lines that are horizontally elongated through the vertical cross-section. The one of the (a) or the (b) laterally overlaps the upper source/drain region and the lower source/drain region. The first gate insulator material has a top that is below a top of the channel region and has a bottom that is above a bottom of the channel region. An upper void space is laterally between the one of the (a) or the (b) and both of the upper source/drain region and the channel region. A lower void space is laterally between the one of the (a) or the (b) and both of the lower source/drain region and the channel region. Second gate insulator material is formed in the upper and lower void spaces. Other embodiments, including structure independent of method, are disclosed. Procédé utilisé dans la formation d'un réseau de transistors verticaux consistant à former des saillies verticales espacées latéralement qui font saillie vers le haut à partir d'un substrat dans une section transversale verticale. Les projections verticales comprennent individuellement une région de source/drain supérieure, une région de source/drain inférieure, et une région de canal verticalement entre celles-ci. Un premier matériau d'isolation de grille est formé le long de parois latérales opposées de la région de canal dans la section transversale verticale. Un premier parmi (a) ou (b) est formée par-dessus des parois latérales opposées du premier matériau d'isolation de grille dans la section transversale verticale, où (a) : des lignes de grille conductrices qui sont allongées horizontalement à travers la section transversale verticale; et (b) : des lignes de grille de remplacement sacrificielles qui sont allongées horizontalement à travers la section transversale verticale. Le premier parmi le (a) ou