GATE DRIVING CIRCUIT AND DISPLAY PANEL

A gate driving circuit and a display panel. The gate driving circuit (100) comprises a plurality of cascaded shift register units (110). The plurality of cascaded shift register units (110) comprise: a first shift register unit (111), comprising a first clock signal end (111A); a (n+1)th shift register unit, comprising a (n+1)th clock signal end; a second shift register unit (112), comprising a second clock signal end (112A); and a (n+2)th shift register unit, comprising a (n+2)th clock signal end. The gate driving circuit (100) further comprises a first clock signal line (CLK1) that is connected to the first clock signal end (111A) and the (n+1)th clock signal end, and a second clock signal line (CLK2) that is connected to the second clock signal end (112A) and the (n+2)th clock signal end; the first clock signal line (CLK1) and the second clock signal line (CLK2) are arranged at an interval; the input end of the first clock signal line (CLK1) is connected to one end of a first resistor (R1); the input end o