METAL-COVERED CHIP SCALE PACKAGES
In some examples, a wafer chip scale package (WCSP) (100) comprises a die (102); multiple electrically conductive terminals (104) coupled to a first surface of the die; and a metal covering (108) abutting five surfaces of the die besides the first surface, each of the five surfaces of the die lying...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | MATSUURA, Masamitsu AOYA, Kengo MASUMOTO, Mutsumi |
| description | In some examples, a wafer chip scale package (WCSP) (100) comprises a die (102); multiple electrically conductive terminals (104) coupled to a first surface of the die; and a metal covering (108) abutting five surfaces of the die besides the first surface, each of the five surfaces of the die lying in a different plane.
Dans certains exemples, selon la présente invention, un boîtier à échelle de puce de tranche (WCSP) (100) comprend une puce (102); de multiples bornes électriquement conductrices (104) couplées à une première surface de la puce; et un revêtement métallique (108) venant en butée sur cinq surfaces de la puce en plus de la première surface, chacune des cinq surfaces de la puce se trouvant dans un plan différent. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_WO2021081477A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>WO2021081477A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_WO2021081477A13</originalsourceid><addsrcrecordid>eNrjZFD0dQ1x9NF19g9zDXJ1UXD28AxQCHZ29HFVCHB09nZ0dw3mYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXx4f5GBkaGBhaGJubmjobGxKkCAH-ZIss</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METAL-COVERED CHIP SCALE PACKAGES</title><source>esp@cenet</source><creator>MATSUURA, Masamitsu ; AOYA, Kengo ; MASUMOTO, Mutsumi</creator><creatorcontrib>MATSUURA, Masamitsu ; AOYA, Kengo ; MASUMOTO, Mutsumi</creatorcontrib><description>In some examples, a wafer chip scale package (WCSP) (100) comprises a die (102); multiple electrically conductive terminals (104) coupled to a first surface of the die; and a metal covering (108) abutting five surfaces of the die besides the first surface, each of the five surfaces of the die lying in a different plane.
Dans certains exemples, selon la présente invention, un boîtier à échelle de puce de tranche (WCSP) (100) comprend une puce (102); de multiples bornes électriquement conductrices (104) couplées à une première surface de la puce; et un revêtement métallique (108) venant en butée sur cinq surfaces de la puce en plus de la première surface, chacune des cinq surfaces de la puce se trouvant dans un plan différent.</description><language>eng ; fre</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210429&DB=EPODOC&CC=WO&NR=2021081477A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210429&DB=EPODOC&CC=WO&NR=2021081477A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MATSUURA, Masamitsu</creatorcontrib><creatorcontrib>AOYA, Kengo</creatorcontrib><creatorcontrib>MASUMOTO, Mutsumi</creatorcontrib><title>METAL-COVERED CHIP SCALE PACKAGES</title><description>In some examples, a wafer chip scale package (WCSP) (100) comprises a die (102); multiple electrically conductive terminals (104) coupled to a first surface of the die; and a metal covering (108) abutting five surfaces of the die besides the first surface, each of the five surfaces of the die lying in a different plane.
Dans certains exemples, selon la présente invention, un boîtier à échelle de puce de tranche (WCSP) (100) comprend une puce (102); de multiples bornes électriquement conductrices (104) couplées à une première surface de la puce; et un revêtement métallique (108) venant en butée sur cinq surfaces de la puce en plus de la première surface, chacune des cinq surfaces de la puce se trouvant dans un plan différent.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD0dQ1x9NF19g9zDXJ1UXD28AxQCHZ29HFVCHB09nZ0dw3mYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXx4f5GBkaGBhaGJubmjobGxKkCAH-ZIss</recordid><startdate>20210429</startdate><enddate>20210429</enddate><creator>MATSUURA, Masamitsu</creator><creator>AOYA, Kengo</creator><creator>MASUMOTO, Mutsumi</creator><scope>EVB</scope></search><sort><creationdate>20210429</creationdate><title>METAL-COVERED CHIP SCALE PACKAGES</title><author>MATSUURA, Masamitsu ; AOYA, Kengo ; MASUMOTO, Mutsumi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2021081477A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MATSUURA, Masamitsu</creatorcontrib><creatorcontrib>AOYA, Kengo</creatorcontrib><creatorcontrib>MASUMOTO, Mutsumi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MATSUURA, Masamitsu</au><au>AOYA, Kengo</au><au>MASUMOTO, Mutsumi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METAL-COVERED CHIP SCALE PACKAGES</title><date>2021-04-29</date><risdate>2021</risdate><abstract>In some examples, a wafer chip scale package (WCSP) (100) comprises a die (102); multiple electrically conductive terminals (104) coupled to a first surface of the die; and a metal covering (108) abutting five surfaces of the die besides the first surface, each of the five surfaces of the die lying in a different plane.
Dans certains exemples, selon la présente invention, un boîtier à échelle de puce de tranche (WCSP) (100) comprend une puce (102); de multiples bornes électriquement conductrices (104) couplées à une première surface de la puce; et un revêtement métallique (108) venant en butée sur cinq surfaces de la puce en plus de la première surface, chacune des cinq surfaces de la puce se trouvant dans un plan différent.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; fre |
| recordid | cdi_epo_espacenet_WO2021081477A1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | METAL-COVERED CHIP SCALE PACKAGES |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T03%3A01%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MATSUURA,%20Masamitsu&rft.date=2021-04-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EWO2021081477A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |