DELAY-LOCKED LOOP (DLL) WITH DIFFERENTIAL DELAY LINES

An integrated circuit is disclosed that implements a delay locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to rece...

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Bibliographische Detailangaben
Hauptverfasser: ASURI, Bhushan Shanti, THIAGARAJAN, Krishnaswamy, MITTAL, Ayush, DEVPUJE, Gajanan Maroti
Format: Patent
Sprache:eng ; fre
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