LOW-POWER-CONSUMPTION HIGH-SPEED ZERO-CURRENT SWITCH

Disclosed is a low-power-consumption high-speed zero-current switch, comprising a delay controller, a driving stage and a power transistor MN. An input end of the delay controller is connected to an external clock (CLK) and an output end thereof is connected to an input end of the driving stage, and an output end of the driving stage is connected to a gate electrode of the power transistor MN. The delay controller comprises a gate signal generator, a sampling circuit and a current controller, these forming a negative feedback loop, such that the source-drain voltage VON and VD a zero-current sampling switch at a moment when same is switched on and a moment when same is switched off are finally stabilized at 0, thereby realizing the source-drain voltage of the power transistor MN being 0 when same is switched on and switched off. Instead of using a high-power-consumption high-speed comparator, the present invention uses a low-power-consumption delay controller so as to generate a switching-on and a switching-o