MULTI LEVEL SYSTEM MEMORY HAVING DIFFERENT CACHING STRUCTURES AND MEMORY CONTROLLER THAT SUPPORTS CONCURRENT LOOK-UP INTO THE DIFFERENT CACHING STRUCTURES

An apparatus is described. The apparatus includes a memory controller to interface to a multi- level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second differen...

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Bibliographische Detailangaben

Hauptverfasser:	GREENFIELD, Zvika, DIAMAND, Israel, MANDELBLAT, Julius Yuli, RUBINSTEIN, Asaf
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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