PIXEL CONNECTION STRUCTURE OF ARRAY SUBSTRATE, AND ARRAY SUBSTRATE
A pixel connection structure of an array substrate, comprising a plurality of data lines (10), the plurality of data lines (10) being arranged in parallel along a first direction; a plurality of gate lines (20) are arranged in parallel along a second direction; the plurality of data lines (10) and t...
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Format: | Patent |
Sprache: | chi ; eng ; fre |
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Zusammenfassung: | A pixel connection structure of an array substrate, comprising a plurality of data lines (10), the plurality of data lines (10) being arranged in parallel along a first direction; a plurality of gate lines (20) are arranged in parallel along a second direction; the plurality of data lines (10) and the plurality of gate lines (20) intersect and define a plurality of sub-pixels (30), the plurality of sub-pixels (30) being arranged in a matrix, each of the sub-pixels (30) comprising a thin film transistor and a pixel electrode, the plurality of sub-pixels (30) comprising a first sub-pixel row (1), a second sub-pixel row (2), a third sub-pixel row (3) and a fourth sub-pixel row (4) which are arranged along the second direction in sequence, the sub-pixels within the first sub-pixel row (1) and the second sub-pixel row (2) being connected to the adjacent data line, the sub-pixels within the third sub-pixel row (3) and the fourth sub-pixel row (4) being connected to the adjacent data line, the data line connected to |
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