INSTRUCTION, CIRCUITS, AND LOGIC FOR GRAPH ANALYTICS ACCELERATION

A processor includes a front end including circuitry to receive and decode an instruction. The instruction is to perform a graph analytic function and pass the instruction to a graph accelerator. The graph accelerator including circuitry to process graph vertices and graph edges as datatypes, execut...

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Bibliographische Detailangaben
Hauptverfasser:	SUNDARAM, Narayanan, WU, Lisa K, HAM, Tae Jun, SATISH, Nadathur Rajagopalan
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	CALCULATING CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
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Beschreibung
Zusammenfassung:	A processor includes a front end including circuitry to receive and decode an instruction. The instruction is to perform a graph analytic function and pass the instruction to a graph accelerator. The graph accelerator including circuitry to process graph vertices and graph edges as datatypes, execute the instruction, and pass results of the instruction to a memory subsystem of the processor. Selon l'invention, un processeur comprend une partie frontale contenant de la circuiterie permettant de recevoir et de décoder une instruction. L'instruction doit effectuer une fonction d'analyse de graphe et transmettre l'instruction à un accélérateur de graphe. L'accélérateur de graphe comprend de la circuiterie servant à traiter des sommets de graphe et des arêtes de graphe en tant que types de données, exécuter l'instruction, et transmettre les résultats de l'instruction à un sous-système de mémoire du processeur.