AVOIDING DEADLOCKS IN PROCESSOR-BASED SYSTEMS EMPLOYING RETRY AND IN-ORDER-RESPONSE NON-RETRY BUS COHERENCY PROTOCOLS

Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a...

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Hauptverfasser:	XU, Kun, RAMIREZ, Cesar, Aaron, TRUONG, Thuong, Quang, SUBRAMANIAM GANASAN, Jaya, Prakash, LE, Hien, Minh
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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