METHODS OF FORMING TRENCHES IN PACKAGES STRUCTURES AND STRUCTURES FORMED THEREBY
Methods of forming package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrat...
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| creator | RAGHAVAN, Prasanna MALATKAR, Pramod YAGNAMURTHY, Naga Sivakumar FEI, Huiyang NICKERSON, Robert |
| description | Methods of forming package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.
L'invention concerne des procédés de formation de structures de boîtier comprenant une tranchée. Un mode de réalisation comprend une première puce disposée sur un premier substrat, et au moins une structure d'interconnexion disposée sur une région périphérique du premier substrat. Un composé de moulage est disposé sur une partie du premier substrat et sur la première puce, une ouverture de tranchée étant disposée dans le composé de moulage qui est situé entre ladite ou lesdites structures d'interconnexion et la première puce. |
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L'invention concerne des procédés de formation de structures de boîtier comprenant une tranchée. Un mode de réalisation comprend une première puce disposée sur un premier substrat, et au moins une structure d'interconnexion disposée sur une région périphérique du premier substrat. Un composé de moulage est disposé sur une partie du premier substrat et sur la première puce, une ouverture de tranchée étant disposée dans le composé de moulage qui est situé entre ladite ou lesdites structures d'interconnexion et la première puce.</description><language>eng ; fre</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161229&DB=EPODOC&CC=WO&NR=2016209475A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161229&DB=EPODOC&CC=WO&NR=2016209475A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RAGHAVAN, Prasanna</creatorcontrib><creatorcontrib>MALATKAR, Pramod</creatorcontrib><creatorcontrib>YAGNAMURTHY, Naga Sivakumar</creatorcontrib><creatorcontrib>FEI, Huiyang</creatorcontrib><creatorcontrib>NICKERSON, Robert</creatorcontrib><title>METHODS OF FORMING TRENCHES IN PACKAGES STRUCTURES AND STRUCTURES FORMED THEREBY</title><description>Methods of forming package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.
L'invention concerne des procédés de formation de structures de boîtier comprenant une tranchée. Un mode de réalisation comprend une première puce disposée sur un premier substrat, et au moins une structure d'interconnexion disposée sur une région périphérique du premier substrat. Un composé de moulage est disposé sur une partie du premier substrat et sur la première puce, une ouverture de tranchée étant disposée dans le composé de moulage qui est situé entre ladite ou lesdites structures d'interconnexion et la première puce.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAjwdQ3x8HcJVvB3U3DzD_L19HNXCAly9XP2cA1W8PRTCHB09nZ0B7KDQ4JCnUNCg4BMRz8XZC5Im6uLQoiHa5CrUyQPA2taYk5xKi-U5mZQdnMNcfbQTS3Ij08tLkhMTs1LLYkP9zcyMDQzMrA0MTd1NDQmThUAThcwRw</recordid><startdate>20161229</startdate><enddate>20161229</enddate><creator>RAGHAVAN, Prasanna</creator><creator>MALATKAR, Pramod</creator><creator>YAGNAMURTHY, Naga Sivakumar</creator><creator>FEI, Huiyang</creator><creator>NICKERSON, Robert</creator><scope>EVB</scope></search><sort><creationdate>20161229</creationdate><title>METHODS OF FORMING TRENCHES IN PACKAGES STRUCTURES AND STRUCTURES FORMED THEREBY</title><author>RAGHAVAN, Prasanna ; MALATKAR, Pramod ; YAGNAMURTHY, Naga Sivakumar ; FEI, Huiyang ; NICKERSON, Robert</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2016209475A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>RAGHAVAN, Prasanna</creatorcontrib><creatorcontrib>MALATKAR, Pramod</creatorcontrib><creatorcontrib>YAGNAMURTHY, Naga Sivakumar</creatorcontrib><creatorcontrib>FEI, Huiyang</creatorcontrib><creatorcontrib>NICKERSON, Robert</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RAGHAVAN, Prasanna</au><au>MALATKAR, Pramod</au><au>YAGNAMURTHY, Naga Sivakumar</au><au>FEI, Huiyang</au><au>NICKERSON, Robert</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHODS OF FORMING TRENCHES IN PACKAGES STRUCTURES AND STRUCTURES FORMED THEREBY</title><date>2016-12-29</date><risdate>2016</risdate><abstract>Methods of forming package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.
L'invention concerne des procédés de formation de structures de boîtier comprenant une tranchée. Un mode de réalisation comprend une première puce disposée sur un premier substrat, et au moins une structure d'interconnexion disposée sur une région périphérique du premier substrat. Un composé de moulage est disposé sur une partie du premier substrat et sur la première puce, une ouverture de tranchée étant disposée dans le composé de moulage qui est situé entre ladite ou lesdites structures d'interconnexion et la première puce.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | METHODS OF FORMING TRENCHES IN PACKAGES STRUCTURES AND STRUCTURES FORMED THEREBY |
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