METHOD FOR EXTRACTING TIME CONSTANT OF GATE DIELECTRIC LAYER TRAP OF SEMICONDUCTOR DEVICE

The present invention relates to the field of microelectronic device reliability. Disclosed is a method for extracting a time constant of a gate dielectric layer trap of a semiconductor device. The method comprises: first initializing a state of a trap in a semiconductor device, to make a final state of the trap be an empty state; then applying a DC signal or an AC signal on a gate terminal, a drain terminal being at zero bias Vd1, respectively applying a small voltage vg2 and vd2 on the gate terminal and the drain terminal after duration t1, and detecting a state of a drain terminal current Id; modifying the duration t1 to be t2=t1+∆t, repeating the last step without changing other conditions, and so on, and performing measurement N times, to obtain t1, t1+∆t t1+(N-1)∆t, and states of the drain terminal current corresponding to N time points; afterwards, performing moving average and calculation, to obtain an occupation probabilities P corresponding to (N-n) time points; and performing fitting by using a for