METHOD AND SYSTEM FOR MAPPING AN INTEGRAL INTO A THREAD OF A PARALLEL ARCHITECTURE
The invention is a method for mapping an integral into a thread of a parallel architecture, in the course of which the integral is mapped into a summation expressed by coefficient values and summation values (S100), and a directed graph is generated corresponding to the computation of the summation...
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Zusammenfassung: | The invention is a method for mapping an integral into a thread of a parallel architecture, in the course of which the integral is mapped into a summation expressed by coefficient values and summation values (S100), and a directed graph is generated corresponding to the computation of the summation (S1 10). The directed graph comprising input nodes corresponding to the coefficient values and to the summation values, being connected to inputs of edges, respectively, and being adapted for giving their values, as intermediate values, to the edges connected thereto with their inputs, at least one intermediate node each corresponding to one operation of the summation, and being connected to outputs of two edges and to an input of one edge, and being adapted for performing the operation on the values of the edges connected thereto with their outputs, and for giving the result of the operation as an intermediate value to the edge connected thereto with its input, and an output node being connected to the output of an edge corresponding to an intermediate value corresponding to at least a part of the summation, and being adapted for receiving the intermediate value thereof. Furthermore, in the course of the method a level of a traversal sequence to each of the nodes is assigned, respectively, (S200), and at each level of the traversal sequence, a storage location of the intermediate value corresponding to the edge connected with its input to the node corresponding to the given level is specified (S300) in a memory corresponding to the thread and comprising a register storage, a local storage, and a global storage. The invention is furthermore a system for mapping an integral into a thread of a parallel architecture.
L'invention concerne un procédé permettant de mapper un chiffre entier dans un fil d'une architecture parallèle, au cours duquel le chiffre entier est mappé dans une sommation exprimée par des valeurs de coefficient et des valeurs de sommation (S100), et un graphe orienté est généré conformément au calcul de la sommation (S110). Le graphe orienté comprend des noeuds d'entrée correspondant aux valeurs de coefficient et aux valeurs de sommation, connectés respectivement aux entrées de bords et conçus pour donner leurs valeurs, en tant que valeurs intermédiaires, aux bords connectés avec leurs entrées, au moins un noeud intermédiaire correspondant à une opération de la sommation, et connectés aux sorties de deux bords et à une entrée d'un bord, et conçus |
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