EFFICIENT LOCKING OF MEMORY PAGES
An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry with...
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| creator | MAKINENI, SRIHARI IYER, RAVISHANKAR RAVI JIANG, XIAOWEI GAO, HONGLIANG FANG, ZHEN |
| description | An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.
L'invention concerne un appareil contenant un coeur de traitement constitué d'un coeur d'unité centrale (UC) et d'au moins un accélérateur couplé au coeur d'UC. Ledit coeur d'UC comprend un pipeline renfermant un répertoire de pages actives (TLB), et un ensemble de circuits logiques pour déterminer un bit de verrouillage dans des données d'attribut d'entrée à l'intérieur de l'entrée du TLB afin de verrouiller une page de mémoire réservée à un accélérateur. |
| format | Patent |
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L'invention concerne un appareil contenant un coeur de traitement constitué d'un coeur d'unité centrale (UC) et d'au moins un accélérateur couplé au coeur d'UC. Ledit coeur d'UC comprend un pipeline renfermant un répertoire de pages actives (TLB), et un ensemble de circuits logiques pour déterminer un bit de verrouillage dans des données d'attribut d'entrée à l'intérieur de l'entrée du TLB afin de verrouiller une page de mémoire réservée à un accélérateur.</description><language>eng ; fre</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131003&DB=EPODOC&CC=WO&NR=2013147882A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131003&DB=EPODOC&CC=WO&NR=2013147882A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MAKINENI, SRIHARI</creatorcontrib><creatorcontrib>IYER, RAVISHANKAR RAVI</creatorcontrib><creatorcontrib>JIANG, XIAOWEI</creatorcontrib><creatorcontrib>GAO, HONGLIANG</creatorcontrib><creatorcontrib>FANG, ZHEN</creatorcontrib><title>EFFICIENT LOCKING OF MEMORY PAGES</title><description>An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.
L'invention concerne un appareil contenant un coeur de traitement constitué d'un coeur d'unité centrale (UC) et d'au moins un accélérateur couplé au coeur d'UC. Ledit coeur d'UC comprend un pipeline renfermant un répertoire de pages actives (TLB), et un ensemble de circuits logiques pour déterminer un bit de verrouillage dans des données d'attribut d'entrée à l'intérieur de l'entrée du TLB afin de verrouiller une page de mémoire réservée à un accélérateur.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFB0dXPzdPZ09QtR8PF39vb0c1fwd1PwdfX1D4pUCHB0dw3mYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXx4f5GBobGhibmFhZGjobGxKkCAIxEIvI</recordid><startdate>20131003</startdate><enddate>20131003</enddate><creator>MAKINENI, SRIHARI</creator><creator>IYER, RAVISHANKAR RAVI</creator><creator>JIANG, XIAOWEI</creator><creator>GAO, HONGLIANG</creator><creator>FANG, ZHEN</creator><scope>EVB</scope></search><sort><creationdate>20131003</creationdate><title>EFFICIENT LOCKING OF MEMORY PAGES</title><author>MAKINENI, SRIHARI ; IYER, RAVISHANKAR RAVI ; JIANG, XIAOWEI ; GAO, HONGLIANG ; FANG, ZHEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2013147882A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MAKINENI, SRIHARI</creatorcontrib><creatorcontrib>IYER, RAVISHANKAR RAVI</creatorcontrib><creatorcontrib>JIANG, XIAOWEI</creatorcontrib><creatorcontrib>GAO, HONGLIANG</creatorcontrib><creatorcontrib>FANG, ZHEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MAKINENI, SRIHARI</au><au>IYER, RAVISHANKAR RAVI</au><au>JIANG, XIAOWEI</au><au>GAO, HONGLIANG</au><au>FANG, ZHEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>EFFICIENT LOCKING OF MEMORY PAGES</title><date>2013-10-03</date><risdate>2013</risdate><abstract>An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.
L'invention concerne un appareil contenant un coeur de traitement constitué d'un coeur d'unité centrale (UC) et d'au moins un accélérateur couplé au coeur d'UC. Ledit coeur d'UC comprend un pipeline renfermant un répertoire de pages actives (TLB), et un ensemble de circuits logiques pour déterminer un bit de verrouillage dans des données d'attribut d'entrée à l'intérieur de l'entrée du TLB afin de verrouiller une page de mémoire réservée à un accélérateur.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | EFFICIENT LOCKING OF MEMORY PAGES |
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