MULTIPHASE BUCK CONVERTER AND MULTIPHASE BUCK CONVERSION METHOD

A multiphase buck converter (10) is disclosed, comprising: - a first buck converter branch (SD1, L1) comprising a first core section (COR1), a first power section (PWR1) having a first output node (LX1), a first coil (11) having a first end connected to the first output node (LX1), the first power s...

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Bibliographische Detailangaben
Hauptverfasser: MILAZZO, PATRIZIA, SEMINARA, MARIA FRANCESCA, MUSUMECI, SALVATORE ROSARIO
Format: Patent
Sprache:eng ; fre
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Zusammenfassung:A multiphase buck converter (10) is disclosed, comprising: - a first buck converter branch (SD1, L1) comprising a first core section (COR1), a first power section (PWR1) having a first output node (LX1), a first coil (11) having a first end connected to the first output node (LX1), the first power section (PWR1) being adapted to be controlled by the first core section (COR1) for providing to the first coil (L1) a first coil current (I1), the first core section (COR1) and the first power section (PWR1) being integrated in a chip (IC); - a second buck converter branch (SD2, L2) comprising a second core section (COR2), a second power section (PWR2) having a second output node (LX2), a second coil (L2) having a first end connected to the second output node (LX2), the second power section (PWR2) being adapted to be controlled by the second core section (COR2) for providing to the second coil (L2) a second coil current (I2), the second core section (COR2) and the second power section (PWR2) being integrated in said chip (IC); - a feedback loop adapted to balance said coil currents (I1,I2). The feedback loop comprises a control block (C_B) that, in order to balance said coil currents, is adapted to compare a first average voltage at the first output node (LX1) with a second average voltage at the second output node (LX2) and control the first (SD1, L1) and second branch (SD2, L2) in order to make said first and second average voltages equal to each other. The control block (C_B) is integrated in said chip (IC) and has a first input directly connected to said first output node (LX1) and a second input directly connected to said second output node (LX2). The control block (C_B) is adapted to directly obtain said first and second average voltages from the instantaneous voltages of the first (LX1) and second (LX2) output nodes. L'invention a trait à un convertisseur abaisseur de tension polyphasé (10) qui comprend : - une première branche (SD1, L1) de convertisseur abaisseur de tension qui comporte une première section coeur (COR1), une première section d'alimentation (PWR1) qui est dotée d'un premier noeud de sortie (LX1), une première bobine (11) qui a une première extrémité connectée au premier noeud de sortie (LX1), la première section d'alimentation (PWR1) étant conçue pour être commandée par la première section coeur (COR1) afin d'alimenter la première bobine (L1) avec un premier courant de bobine (I1), et la première section coeur (COR1) ainsi que la première