MULTI-HOST NAND FLASH CONTROLLER

Described herein is a multi-host computing system (200) having multiple host processors running different operating systems. The described multi-host computing system (200) comprises a multi-host NAND flash controller (202) to allow sharing of a NAND flash device (108) among the multiple host proces...

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Bibliographische Detailangaben
Hauptverfasser:	VOLETI, SIVA RAGHURAM, KANIGICHERLA, BALAJI, TANDABOINA, KRISHNA MOHAN
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	CALCULATING CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS INFORMATION STORAGE PHYSICS STATIC STORES TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
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Beschreibung
Zusammenfassung:	Described herein is a multi-host computing system (200) having multiple host processors running different operating systems. The described multi-host computing system (200) comprises a multi-host NAND flash controller (202) to allow sharing of a NAND flash device (108) among the multiple host processors. The described multi-host NAND flash controller (202) may include host interaction components, host command switching logic (310), and NAND command logic (316) to enable sharing of the NAND flash device (108). L'invention concerne un système de calcul multi-hôte (200) possédant de multiples processeurs hôtes utilisant différents systèmes d'exploitations. Le système de calcul multi-hôte (200) comporte un contrôleur flash NAND multi-hôte (202) permettant le partage d'un dispositif flash NAND (108) entre les multiples processeurs hôtes. Le contrôleur flash NAND multi-hôte (202) peut comprendre des composants d'interaction hôtes, un circuit logique de commutation de commande hôte (310) et un circuit de commande NAND (316) permettant le partage du dispositif flash NAND (108).