PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP, METHODS FOR FABRICATING SUCH PRODUCT CHIPS AND DIE, AND METHODS FOR READING A FEATURE PATTERN FROM A PACKAGED DIE
Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features (85) formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features (80-84)...
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Format: | Patent |
Sprache: | eng ; fre |
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