FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY
In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the s...
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| creator | LOKE, MUN LEONG MONG, WENG KHOON ONG, TEAN WEE LIM, BOK SIM RUDGE, A VETHANAYAGAM ONG, KANG EU LIM, SIH FEI |
| description | In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
L'invention concerne, dans certains modes de réalisation, le placage anélectrolytique pour substrats électroniques. Dans cette optique, elle présente un procédé consistant à recevoir une bande de substrat sans noyau, à attacher des billes de brasure à l'arrière de la bande de substrat sans noyau et à former un moule rigidifiant arrière parmi les billes de brasure. L'invention concerne aussi d'autres modes de réalisation. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_WO2010002739A3</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>WO2010002739A3</sourcerecordid><originalsourceid>FETCH-epo_espacenet_WO2010002739A33</originalsourceid><addsrcrecordid>eNrjZAh28_EMUHD2ABKOwcGuvk4-kQoBQf7OrsHBCm7-QQqhPiFBjgohHp5-CsGhTsFAToirgqOfi0KAo7O3o7urgr8fnAkzgIeBNS0xpziVF0pzMyi7uYY4e-imFuTHpxYXJCan5qWWxIf7GxkYGhgYGJkbWzoaGxOnCgCaIzBz</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY</title><source>esp@cenet</source><creator>LOKE, MUN LEONG ; MONG, WENG KHOON ; ONG, TEAN WEE ; LIM, BOK SIM ; RUDGE, A VETHANAYAGAM ; ONG, KANG EU ; LIM, SIH FEI</creator><creatorcontrib>LOKE, MUN LEONG ; MONG, WENG KHOON ; ONG, TEAN WEE ; LIM, BOK SIM ; RUDGE, A VETHANAYAGAM ; ONG, KANG EU ; LIM, SIH FEI</creatorcontrib><description>In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
L'invention concerne, dans certains modes de réalisation, le placage anélectrolytique pour substrats électroniques. Dans cette optique, elle présente un procédé consistant à recevoir une bande de substrat sans noyau, à attacher des billes de brasure à l'arrière de la bande de substrat sans noyau et à former un moule rigidifiant arrière parmi les billes de brasure. L'invention concerne aussi d'autres modes de réalisation.</description><language>eng ; fre</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100325&DB=EPODOC&CC=WO&NR=2010002739A3$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100325&DB=EPODOC&CC=WO&NR=2010002739A3$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LOKE, MUN LEONG</creatorcontrib><creatorcontrib>MONG, WENG KHOON</creatorcontrib><creatorcontrib>ONG, TEAN WEE</creatorcontrib><creatorcontrib>LIM, BOK SIM</creatorcontrib><creatorcontrib>RUDGE, A VETHANAYAGAM</creatorcontrib><creatorcontrib>ONG, KANG EU</creatorcontrib><creatorcontrib>LIM, SIH FEI</creatorcontrib><title>FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY</title><description>In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
L'invention concerne, dans certains modes de réalisation, le placage anélectrolytique pour substrats électroniques. Dans cette optique, elle présente un procédé consistant à recevoir une bande de substrat sans noyau, à attacher des billes de brasure à l'arrière de la bande de substrat sans noyau et à former un moule rigidifiant arrière parmi les billes de brasure. L'invention concerne aussi d'autres modes de réalisation.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAh28_EMUHD2ABKOwcGuvk4-kQoBQf7OrsHBCm7-QQqhPiFBjgohHp5-CsGhTsFAToirgqOfi0KAo7O3o7urgr8fnAkzgIeBNS0xpziVF0pzMyi7uYY4e-imFuTHpxYXJCan5qWWxIf7GxkYGhgYGJkbWzoaGxOnCgCaIzBz</recordid><startdate>20100325</startdate><enddate>20100325</enddate><creator>LOKE, MUN LEONG</creator><creator>MONG, WENG KHOON</creator><creator>ONG, TEAN WEE</creator><creator>LIM, BOK SIM</creator><creator>RUDGE, A VETHANAYAGAM</creator><creator>ONG, KANG EU</creator><creator>LIM, SIH FEI</creator><scope>EVB</scope></search><sort><creationdate>20100325</creationdate><title>FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY</title><author>LOKE, MUN LEONG ; MONG, WENG KHOON ; ONG, TEAN WEE ; LIM, BOK SIM ; RUDGE, A VETHANAYAGAM ; ONG, KANG EU ; LIM, SIH FEI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2010002739A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LOKE, MUN LEONG</creatorcontrib><creatorcontrib>MONG, WENG KHOON</creatorcontrib><creatorcontrib>ONG, TEAN WEE</creatorcontrib><creatorcontrib>LIM, BOK SIM</creatorcontrib><creatorcontrib>RUDGE, A VETHANAYAGAM</creatorcontrib><creatorcontrib>ONG, KANG EU</creatorcontrib><creatorcontrib>LIM, SIH FEI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LOKE, MUN LEONG</au><au>MONG, WENG KHOON</au><au>ONG, TEAN WEE</au><au>LIM, BOK SIM</au><au>RUDGE, A VETHANAYAGAM</au><au>ONG, KANG EU</au><au>LIM, SIH FEI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY</title><date>2010-03-25</date><risdate>2010</risdate><abstract>In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.
L'invention concerne, dans certains modes de réalisation, le placage anélectrolytique pour substrats électroniques. Dans cette optique, elle présente un procédé consistant à recevoir une bande de substrat sans noyau, à attacher des billes de brasure à l'arrière de la bande de substrat sans noyau et à former un moule rigidifiant arrière parmi les billes de brasure. L'invention concerne aussi d'autres modes de réalisation.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY |
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