EMBEDDED STRUCTURE FOR PASSIVATION INTEGRITY TESTING

The present invention relates to a method and system for testing integrity of a passivation layer (108) covering a semiconductor device. A structured layer of electrically conducting material (104) is deposited onto at least a portion of a top surface of a substrate (102) of the semiconductor device...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	ROUSSEVILLE, LUCIE, A, SEBASTIEN, JACQUELINE, GAMAND, PATRICE, YON, DOMINQUE
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING
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