SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP

A method for performing timing optimization of a detailed routed netlist (100), incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, an...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	KOTECHA, POOJA, M, VILLARRUBIA, PAUL, G, MATHENY, ADAM, P, KAZDA, MICHAEL, A, REDDY, LAKSHMI, TREVILLYAN, LOUISE, H
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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