SYSTEM AND METHOD FOR AN EFFICIENT COMPARISON OPERATION OF MULTI-BIT VECTORS IN A DIGITAL LOGIC CIRCUIT

An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by recei...

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Format: Patent
Sprache:eng ; fre
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Zusammenfassung:An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A [N-1 :0] and a second N-bit vectorB [N- 1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N-L0] & ~B[N-J: 0]) operation using A[N-L0] and ~ L'invention concerne une technique améliorée réduisant considérablement la logique et le temps de calcul nécessaires pour déterminer si la différence entre deux vecteurs multibits est égale à un nombre donné, ou se trouve entre deux nombres donnés dans un circuit logique numérique. Dans un mode de réalisation en exemple, ceci est accompli en recevant un premier vecteur à N-bits