STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES
A semiconductor workpiece including a substrate 10, a relaxed buffer layer 14, 18 including a graded portion formed on the substrate, and at least one strained transitional layer 16 within the graded portion of the relaxed buffer layer 14, 18 and method of manufacturing the same. The at least one st...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | FIGUET, CHRISTOPHE CODY, NYLES, W KENNARD, MARK |
| description | A semiconductor workpiece including a substrate 10, a relaxed buffer layer 14, 18 including a graded portion formed on the substrate, and at least one strained transitional layer 16 within the graded portion of the relaxed buffer layer 14, 18 and method of manufacturing the same. The at least one strained transitional layer 16 reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer 14, 18 relative to CTE contraction of the substrate 10.
La présente invention concerne une pièce à usiner semi-conductrice comprenant un substrat 10, une couche tampon non contrainte 14, 18 comprenant une partie à gradient disposée sur le substrat, et au moins une couche de transition contrainte 16 à l'intérieur de la partie à gradient de la couche tampon non contrainte 14, 18 et son procédé de fabrication. La ou les couche(s) de transition contrainte(s) 16 permet(tent) de réduire une proportion de la courbure de la pièce à usiner provoquée par la contraction du coefficient d'expansion thermique (CTE) différentiel de la couche tampon non contrainte 14, 18 par rapport à la contraction du CTE du substrat 10. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_WO2008014079A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>WO2008014079A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_WO2008014079A13</originalsourceid><addsrcrecordid>eNrjZDALDgly9PRzdVHwcYx0DQpWCPcM8fD0Uwh29fV09vdzCXUO8Q9ScAp1c3MNUgCqBfJDg1yDeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfLi_kYGBhYGhiYG5paOhMXGqAPKrKWU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES</title><source>esp@cenet</source><creator>FIGUET, CHRISTOPHE ; CODY, NYLES, W ; KENNARD, MARK</creator><creatorcontrib>FIGUET, CHRISTOPHE ; CODY, NYLES, W ; KENNARD, MARK</creatorcontrib><description>A semiconductor workpiece including a substrate 10, a relaxed buffer layer 14, 18 including a graded portion formed on the substrate, and at least one strained transitional layer 16 within the graded portion of the relaxed buffer layer 14, 18 and method of manufacturing the same. The at least one strained transitional layer 16 reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer 14, 18 relative to CTE contraction of the substrate 10.
La présente invention concerne une pièce à usiner semi-conductrice comprenant un substrat 10, une couche tampon non contrainte 14, 18 comprenant une partie à gradient disposée sur le substrat, et au moins une couche de transition contrainte 16 à l'intérieur de la partie à gradient de la couche tampon non contrainte 14, 18 et son procédé de fabrication. La ou les couche(s) de transition contrainte(s) 16 permet(tent) de réduire une proportion de la courbure de la pièce à usiner provoquée par la contraction du coefficient d'expansion thermique (CTE) différentiel de la couche tampon non contrainte 14, 18 par rapport à la contraction du CTE du substrat 10.</description><language>eng ; fre</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080131&DB=EPODOC&CC=WO&NR=2008014079A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080131&DB=EPODOC&CC=WO&NR=2008014079A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FIGUET, CHRISTOPHE</creatorcontrib><creatorcontrib>CODY, NYLES, W</creatorcontrib><creatorcontrib>KENNARD, MARK</creatorcontrib><title>STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES</title><description>A semiconductor workpiece including a substrate 10, a relaxed buffer layer 14, 18 including a graded portion formed on the substrate, and at least one strained transitional layer 16 within the graded portion of the relaxed buffer layer 14, 18 and method of manufacturing the same. The at least one strained transitional layer 16 reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer 14, 18 relative to CTE contraction of the substrate 10.
La présente invention concerne une pièce à usiner semi-conductrice comprenant un substrat 10, une couche tampon non contrainte 14, 18 comprenant une partie à gradient disposée sur le substrat, et au moins une couche de transition contrainte 16 à l'intérieur de la partie à gradient de la couche tampon non contrainte 14, 18 et son procédé de fabrication. La ou les couche(s) de transition contrainte(s) 16 permet(tent) de réduire une proportion de la courbure de la pièce à usiner provoquée par la contraction du coefficient d'expansion thermique (CTE) différentiel de la couche tampon non contrainte 14, 18 par rapport à la contraction du CTE du substrat 10.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDALDgly9PRzdVHwcYx0DQpWCPcM8fD0Uwh29fV09vdzCXUO8Q9ScAp1c3MNUgCqBfJDg1yDeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfLi_kYGBhYGhiYG5paOhMXGqAPKrKWU</recordid><startdate>20080131</startdate><enddate>20080131</enddate><creator>FIGUET, CHRISTOPHE</creator><creator>CODY, NYLES, W</creator><creator>KENNARD, MARK</creator><scope>EVB</scope></search><sort><creationdate>20080131</creationdate><title>STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES</title><author>FIGUET, CHRISTOPHE ; CODY, NYLES, W ; KENNARD, MARK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2008014079A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>FIGUET, CHRISTOPHE</creatorcontrib><creatorcontrib>CODY, NYLES, W</creatorcontrib><creatorcontrib>KENNARD, MARK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FIGUET, CHRISTOPHE</au><au>CODY, NYLES, W</au><au>KENNARD, MARK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES</title><date>2008-01-31</date><risdate>2008</risdate><abstract>A semiconductor workpiece including a substrate 10, a relaxed buffer layer 14, 18 including a graded portion formed on the substrate, and at least one strained transitional layer 16 within the graded portion of the relaxed buffer layer 14, 18 and method of manufacturing the same. The at least one strained transitional layer 16 reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer 14, 18 relative to CTE contraction of the substrate 10.
La présente invention concerne une pièce à usiner semi-conductrice comprenant un substrat 10, une couche tampon non contrainte 14, 18 comprenant une partie à gradient disposée sur le substrat, et au moins une couche de transition contrainte 16 à l'intérieur de la partie à gradient de la couche tampon non contrainte 14, 18 et son procédé de fabrication. La ou les couche(s) de transition contrainte(s) 16 permet(tent) de réduire une proportion de la courbure de la pièce à usiner provoquée par la contraction du coefficient d'expansion thermique (CTE) différentiel de la couche tampon non contrainte 14, 18 par rapport à la contraction du CTE du substrat 10.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; fre |
| recordid | cdi_epo_espacenet_WO2008014079A1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T09%3A17%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=FIGUET,%20CHRISTOPHE&rft.date=2008-01-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EWO2008014079A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |