SYSTEM AND METHOD FOR MODELING, ABSTRACTION, AND ANALYSIS OF SOFTWARE
A system and method is disclosed for formal verification of software that advantageously translates the software (101), which can have bounded recursion, into a Boolean representation (130) comprised of basic blocks and which applies SAT-based model checking (150) to the Boolean representation. L�...
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| Format: | Patent |
| Sprache: | eng ; fre |
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| Zusammenfassung: | A system and method is disclosed for formal verification of software that advantageously translates the software (101), which can have bounded recursion, into a Boolean representation (130) comprised of basic blocks and which applies SAT-based model checking (150) to the Boolean representation.
L'invention concerne un système et un procédé de vérification de programmes logiciels convertissant avantageusement un logiciel, qui peut avoir une récursivité limitée, en une représentation booléenne constituée d'unités de base, et appliquant un modèle de type SAT destiné à vérifier la représentation booléenne. |
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