A RECONFIGURABLE DIGITAL PROCESSING SYSTEM FOR SPACE

A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM- based FPGA as a signal processor. In one embodiment, multiple FPGAs are connected together to provide the necessary processing function. Flexibility in reconfiguration includes the utilizing of a timing and synchronization block as well as a common configuration block which when coupled to an interconnect block permits reconfiguration of a customizable application core, depending o the particular signal processing function desired. The result is that damaged or inoperable signal processing components can be repaired in space without having to physically attend to the hardware by transmitting to the spacecraft commands which reconfigure the particular FPGAs thus to alter their signal processing function. Also mission changes can be accomplished by reprogramming the FPGAs. L'invention concerne un système de traitement numérique reconfigurable destiné à des applications spatiales. Ce système utilise des prédiffusés programmables (FPGA) d'après une approche centrée sur le matériel pour reconfigurer des processeurs de logiciels dans un véhicule spatial par reprogrammation de FPGA multiples de façon à obtenir une caractéristique puissance/performance pour des tâches de traitement de signal qui ne peuvent pas être exécutées par simple utilisation de processeurs prêts à l'emploi. Selon un mode de réalisation, lorsque des processeurs de signal sont endommagés ou inutilisables sur un engin spatial, les processeurs restants non endommagés peuvent être reconfigurés par modification du langage machine et du binaire au niveau des FPGA pour modifier le processeur central tout en conservant les composants non endommagés de sorte que les fonctions de traitement de signal