PROCESS FOR THE FABRICATION OF MOSFET DEVICES DEPLETION, SILICIDED SOURCE AND DRAIN JUNCTIONS
A sub-0.1 mu m MOSFET device having minimum poly depletion, silicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene- gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy...
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| creator | BOYD, DIANE, CATHERINE HANAFI, HUSSEIN, IBRAHIM ROY, RONNEN, ANDREW BRODSKY, STEPHEN, BRUCE |
| description | A sub-0.1 mu m MOSFET device having minimum poly depletion, silicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene- gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
La présente invention concerne un MOSFET sub-0,1 ñm à déplétion minimale du silicium polycristallin et à jonctions source et drain siliciurées, et comportant des portes de silicium polycristallin à très faible résistance de couche. On a recours, à cet effet, à un damascénage des portes aboutissant, dès l'implantation, à l'annelage et la siliciuration des sources et drains en présence d'une région de porte fictive qui disparaîtra ensuite au profit d'une région à porte au silicium polycristallin. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_WO0227799A3</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>WO0227799A3</sourcerecordid><originalsourceid>FETCH-epo_espacenet_WO0227799A33</originalsourceid><addsrcrecordid>eNqNzEEKwjAQheFsXIh6hzmAgrSL0mVMJnSkZkqmrSspReJKtFDvjyl4AFf_4n28tbo1gQ2KgOMAbYXg9CmQ0S2xB3ZwYXHYgsWeEkttaly2PQjVZMiiBeEuGATtLdigycO582ZBslWrx_ic4-7XjYL0ZqpDnN5DnKfxHl_xM1z5mGVFUZY6z_8gX2rnMjI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PROCESS FOR THE FABRICATION OF MOSFET DEVICES DEPLETION, SILICIDED SOURCE AND DRAIN JUNCTIONS</title><source>esp@cenet</source><creator>BOYD, DIANE, CATHERINE ; HANAFI, HUSSEIN, IBRAHIM ; ROY, RONNEN, ANDREW ; BRODSKY, STEPHEN, BRUCE</creator><creatorcontrib>BOYD, DIANE, CATHERINE ; HANAFI, HUSSEIN, IBRAHIM ; ROY, RONNEN, ANDREW ; BRODSKY, STEPHEN, BRUCE</creatorcontrib><description>A sub-0.1 mu m MOSFET device having minimum poly depletion, silicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene- gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
La présente invention concerne un MOSFET sub-0,1 ñm à déplétion minimale du silicium polycristallin et à jonctions source et drain siliciurées, et comportant des portes de silicium polycristallin à très faible résistance de couche. On a recours, à cet effet, à un damascénage des portes aboutissant, dès l'implantation, à l'annelage et la siliciuration des sources et drains en présence d'une région de porte fictive qui disparaîtra ensuite au profit d'une région à porte au silicium polycristallin.</description><edition>7</edition><language>eng ; fre</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021121&DB=EPODOC&CC=WO&NR=0227799A3$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021121&DB=EPODOC&CC=WO&NR=0227799A3$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BOYD, DIANE, CATHERINE</creatorcontrib><creatorcontrib>HANAFI, HUSSEIN, IBRAHIM</creatorcontrib><creatorcontrib>ROY, RONNEN, ANDREW</creatorcontrib><creatorcontrib>BRODSKY, STEPHEN, BRUCE</creatorcontrib><title>PROCESS FOR THE FABRICATION OF MOSFET DEVICES DEPLETION, SILICIDED SOURCE AND DRAIN JUNCTIONS</title><description>A sub-0.1 mu m MOSFET device having minimum poly depletion, silicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene- gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
La présente invention concerne un MOSFET sub-0,1 ñm à déplétion minimale du silicium polycristallin et à jonctions source et drain siliciurées, et comportant des portes de silicium polycristallin à très faible résistance de couche. On a recours, à cet effet, à un damascénage des portes aboutissant, dès l'implantation, à l'annelage et la siliciuration des sources et drains en présence d'une région de porte fictive qui disparaîtra ensuite au profit d'une région à porte au silicium polycristallin.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzEEKwjAQheFsXIh6hzmAgrSL0mVMJnSkZkqmrSspReJKtFDvjyl4AFf_4n28tbo1gQ2KgOMAbYXg9CmQ0S2xB3ZwYXHYgsWeEkttaly2PQjVZMiiBeEuGATtLdigycO582ZBslWrx_ic4-7XjYL0ZqpDnN5DnKfxHl_xM1z5mGVFUZY6z_8gX2rnMjI</recordid><startdate>20021121</startdate><enddate>20021121</enddate><creator>BOYD, DIANE, CATHERINE</creator><creator>HANAFI, HUSSEIN, IBRAHIM</creator><creator>ROY, RONNEN, ANDREW</creator><creator>BRODSKY, STEPHEN, BRUCE</creator><scope>EVB</scope></search><sort><creationdate>20021121</creationdate><title>PROCESS FOR THE FABRICATION OF MOSFET DEVICES DEPLETION, SILICIDED SOURCE AND DRAIN JUNCTIONS</title><author>BOYD, DIANE, CATHERINE ; HANAFI, HUSSEIN, IBRAHIM ; ROY, RONNEN, ANDREW ; BRODSKY, STEPHEN, BRUCE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO0227799A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BOYD, DIANE, CATHERINE</creatorcontrib><creatorcontrib>HANAFI, HUSSEIN, IBRAHIM</creatorcontrib><creatorcontrib>ROY, RONNEN, ANDREW</creatorcontrib><creatorcontrib>BRODSKY, STEPHEN, BRUCE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BOYD, DIANE, CATHERINE</au><au>HANAFI, HUSSEIN, IBRAHIM</au><au>ROY, RONNEN, ANDREW</au><au>BRODSKY, STEPHEN, BRUCE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PROCESS FOR THE FABRICATION OF MOSFET DEVICES DEPLETION, SILICIDED SOURCE AND DRAIN JUNCTIONS</title><date>2002-11-21</date><risdate>2002</risdate><abstract>A sub-0.1 mu m MOSFET device having minimum poly depletion, silicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene- gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
La présente invention concerne un MOSFET sub-0,1 ñm à déplétion minimale du silicium polycristallin et à jonctions source et drain siliciurées, et comportant des portes de silicium polycristallin à très faible résistance de couche. On a recours, à cet effet, à un damascénage des portes aboutissant, dès l'implantation, à l'annelage et la siliciuration des sources et drains en présence d'une région de porte fictive qui disparaîtra ensuite au profit d'une région à porte au silicium polycristallin.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| title | PROCESS FOR THE FABRICATION OF MOSFET DEVICES DEPLETION, SILICIDED SOURCE AND DRAIN JUNCTIONS |
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