Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages

In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of VCC-Vth, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of +E,fra 1/2+EE xVCC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.