Shared interrupt multi-core architecture for low power applications
A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.
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| creator | Echeverri Escobar, Juan Diego Pineda de Gyvez, Jose de Jesus |
| description | A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks. |
| format | Patent |
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| language | eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Shared interrupt multi-core architecture for low power applications |
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