Shared interrupt multi-core architecture for low power applications

Shared interrupt multi-core architecture for low power applications

A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.

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Bibliographische Detailangaben
Hauptverfasser: Echeverri Escobar, Juan Diego, Pineda de Gyvez, Jose de Jesus
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.