Slicer and decision feedback equalization circuitry

One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out...

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Bibliographische Detailangaben
Hauptverfasser:	Eitan, Ro'ee, Lazar, Dror, Pogrebinsky, Alexander, Livne, Ram, Fael, Tomer, Krupnik, Yoel, Tsirkin, Vladislav, Cohen, Ariel, Ran, Adee Ofir
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CONTROL OF AMPLIFICATION ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.