Implementing hardware accelerator for storage write cache management with cache line manipulation

Implementing hardware accelerator for storage write cache management with cache line manipulation

A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management....

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Bakke Brian E, Edwards Joseph R, Radhakrishnan Gowrisankar, Gerhard Adrian C, Moertl Daniel F, Galbraith Robert E, Weckwerth Rick A
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs hardware manipulation of CLs (Cache Lines), a hash table, and per array LRU queues.