Memory circuitry with row-wise gating capabilities

An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell in the array may be a single-port or a multiport memory cell. Memory cells in the same column of the array are connected to shared bit lines, whereas memory cells in the same row of the array are...

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Bibliographische Detailangaben

1. Verfasser:	Duong Kenneth
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
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