Memory circuitry with row-wise gating capabilities

An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell in the array may be a single-port or a multiport memory cell. Memory cells in the same column of the array are connected to shared bit lines, whereas memory cells in the same row of the array are...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Duong Kenneth
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell in the array may be a single-port or a multiport memory cell. Memory cells in the same column of the array are connected to shared bit lines, whereas memory cells in the same row of the array are connected to shared word lines. The memory cells in the same row may also be connected to a row control line. During normal operations, the row control line may provide a positive power supply voltage to each memory cell along that row. During write operations, the row control line may be driven to ground or tri-stated to help improve the write margin and the write performance of the selected memory cells. The aspect ratio of these memory cells may also be more square-like or balanced to help improve power delivery.