Apparatus and method for reduced latency signal synchronization

A circuit to sample an input signal in an asynchronous clock domain. The apparatus includes a first latch configured to favor resolving to a logical high level and a second latch configured to favor resolving to a logical low level. The circuit includes a pullup pMOSFET, and first and second pMOSFETs. The first pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to a first input port of the first latch, and a drain terminal coupled to a second output port of the second latch. The second pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to the second output port of the second latch, and a drain terminal coupled to the first input port of the first latch.