Synchronizer with a timing closure enhancement

Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput.