Methods for designing a layout of a semiconductor device including at least one risk via

A method of designing a layout of a semiconductor device includes preparing a layout for a semiconductor integrated circuit, the preparing of the layout including providing lower and upper metal patterns and via patterns, which are vertically interposed between the lower and upper metal patterns, performing a retargeting process on the lower and upper metal patterns, classifying the via patterns to extract at least one risk via from the via patterns and changing a position of the risk via. During the changing of the position of the risk via, all of the via patterns, other than the risk via, are unchanged in position thereof. Related systems and computer program products are disclosed.