Substrate structure for packaging chip

A substrate structure including a carrier and a substrate is provided. The carrier includes a release layer, a dielectric layer and a metal layer. The dielectric layer is disposed between the release layer and the metal layer. The substrate includes a packaging region and a peripheral region. The pe...

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Bibliographische Detailangaben
Hauptverfasser:	Lin Kuo-Tung, Huang Yu-Chi
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY LAYERED PRODUCTS LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PERFORMING OPERATIONS PRINTED CIRCUITS SEMICONDUCTOR DEVICES TRANSPORTING
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Beschreibung
Zusammenfassung:	A substrate structure including a carrier and a substrate is provided. The carrier includes a release layer, a dielectric layer and a metal layer. The dielectric layer is disposed between the release layer and the metal layer. The substrate includes a packaging region and a peripheral region. The peripheral region is connected to the packaging region and surrounds the packaging region. The peripheral region or the packaging region has a plurality of through holes. The substrate is disposed on the carrier. The release layer is located between the substrate and the dielectric layer. The release layer and the dielectric layer are filled in the through hole such that the substrate is separably attached to the carrier.