Distributed mechanism for clock and reset control in a microprocessor

Implementations of the present disclosure involve a system and/or method for implementing a reset controller of a microprocessor or other type of computing system by connecting the reset controller to a reset controller bus or other type of general purpose bus. Through the reset bus, the reset controller signals used to generate the reset sequence of the system may be transmitted to the components of the system through a bus, rather than utilizing a direct wire connection between the components and the reset controller. The wires that comprise the reset bus may then be run to one or more components of the microprocessor design that are restarted during the reset sequence. Each of these components may also include a reset controller circuit that is designed to receive the reset control signals from the reset controller and decode the signals to determine if the received signal applies to the component.