Interface circuits configured to interface with multi-rank memory

An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Nam Yoonjee, Yi Shinyoung, Chae Kwanyeob, Oh Ji Hun, Choi Jong-Ryun
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.