Unequal error correction code in multi-track recording

Systems and methods are disclosed for implementing unequal error correction code (ECC) in multi-track recording. A device may comprise a circuit configured to implement an error correction coding scheme applying different code rate error correction codes on adjacent tracks within a same recording zone. The circuit may perform a read operation, including simultaneously detecting bits from a first track and a second track of the adjacent tracks, iteratively applying detected bits from the first track to perform adjacent track interference cancellation (ATIC) to decode bits from the second track, and iteratively applying detected bits from the second track to perform ATIC to decode bits from the first track.